nb3w800lmng技术资料-NB3W800L3.3V100133MHz.PDF

NB3W800L 3.3 V 100/133 MHz Differential 1:8 HCSL- Compatible Push-Pull Clock ZDB/Fanout Buffer for PCIe Description The NB3W800L is a low−power 8−output differential buffer that MARKING meets all the performance requirements of the DB800ZL DIAGRAM specification. The NB3W800L is capable of distributing the reference 1 clocks for Intel® QuickPath Interconnect (Intel QPI and UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel Scalable Memory NB3W800L 1 48 Interconnect (Intel SMI) applications. A fixed, internal feedback path AWLYYWWG maintains low drift for critical QPI applications. CASE 485DP Features • 8 Differential Clock Output Pairs @ 0.7 V NB3W800L = Specific Device Code A = Assembly Location • Low−power NMOS Push−pull HCSL Compatible Outputs WL = Wafer Lot • Cycle−to−cycle Jitter 50 ps YY = Year WW = Work Week • Output−to−output Skew 50 ps G = Pb−Free Package • Input−to−output Delay Variation 100 ps • PCIe Phase Jitter: Gen3 1.0 ps, Gen4 0.5 ps RMS • QPI 9.6GT/s 12UI Phase J