基于VerilogHDL的有限状态机的优化设计.pdf

基于Verilog HDL 的有限状态机的优化设计 电子质量 （2012 第03 期） 基于Verilog HDL 的有限状态机的优化设计 Optimization Design of FSM Based on Verilog HDL 罗翔,李娇龙, 田正凯（成都理工大学核技术与自动化工程学院, 四川 成都610059） Luo Xiang,Li Jiao- long,Tian Zheng- kai(Chengdu University of Technology,The College of Nuclear Technology and Automation Engineering,Sichuan Chengdu 610059） 摘 要：有限状态机(FSM)在数字电路设计中的使用非常广泛，该文研究了有限状态机的优化设计方 法。利用FPGA 开发软件Quartus II 和仿真软件ModelSim- Altera 对不同方法所设计的状态机进行综 合电路分析以及对仿真波形进行时序分析，找出不同状态机在电路上、仿真中以及稳定性上的优缺 点。结果表明，采用两段式(Two- always)和三段式(Three- always)设计的状态机在多方面上都优于用一 段式(One- always)所设计的状态机，而且采用三段式所设计的状态机在稳定性上更优于用两段式所 设计的状态机。 关键词：Verilog HDL；有限状态机；Quartus II ；优化设计 中图分类号：TN402 文献标识码：A 文章编号：1003- 0107(2012)03- 0036- 04 Abstract: FSM is widely used in digital circuit design.Optimization design method of FSM is intro- duced.Use FPGA development software Quartus II and simulation software to analyze the synthetical circuit of FSM designed by different methods and analyze the time sequence of simulation waveforms. Find out Advantages and disadvantages on circuit,simulation and stability of different FSMs.According the result,the FSM designed by Two- always method and Three- always method is better than that de- signed by One- always method on many aspects.And three- always FSM is better than two- always FSM on stability. Key w ords: Verilog HDL;FSM(Finite State Machine);Quartus II;Optimization design CLC number: TN402 Document code:A Article ID ：1003-