数字钟电路原理图程序.docVIP

数字钟电路原理图程序清单 ********顶层程序描述*********** 程序：TIMER_SET.VHD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity timer_set is port(cp:in std_logic; --CLOCK segout:out std_logic_vector(7 downto 0); --SEG7 DISPLAY O/P selout:out std_logic_vector(5 downto 0); --SELECT SEG7 O/P numout:out std_logic_vector(3 downto 0); --NUMBER DISPLAY SIGNAL key:in std_logic_vector(2downto0)); --TIMERADJUSTCLR end timer_set; architecture behavioral of timer_set is component counter60 port(cp :in std_logic; bin :out std_logic_vector(5 downto 0); s :in std_logic; clr :in std_logic; ec :in std_logic; cy60:out std_logic); end component; component counter24 port(cp :in std_logic; bin :out std_logic_vector(5 downto 0); s :in std_logic; clr :in std_logic; ec :in std_logic; cy24:out std_logic); end component; component free_counter port(cp :in std_logic; dbs :in std_logic_vector(5 downto 0); dbm :in std_logic_vector(5 downto 0); dbh :in std_logic_vector(5 downto 0); state :in std_logic_vector(1 downto 0); sec :out std_logic; sample :out std_logic; glitter:out std_logic; bin :out std_logic_vector(5 downto 0); enb :out std_logic_vector(2 downto 0); sel :out std_logic_vector(5 downto 0); match :out std_logic; s :out std_logic_vector(2 downto 0)); end component; component binary_bcd port(bin:in std_logic_vector(5 downto 0);