An FPGA based Object Detector.pdfVIP

An FPGA-based Object Detector with Dynamic Workload Balancing Chuan Cheng #1 , Christos-Savvas Bouganis #2 # Department of Electrical and Electronic Engineering, Imperial College London Exhibition Road, South Kensington, London, UK, SW7 2AZ 1 chuan.cheng09@imperial.ac.uk 2 christos-savvas.bouganis@imperial.ac.uk Abstract—In recent years, object detection has been more Image frequently integrated with other vision processing functions, patch Pass acting for acquisition of region of interest and is widely adopted Stage 1 Stage 2 Stage 3 in portable devices such as digital camera capable for automatic focusing on faces. In applications targeting those devices, limi- Fail Fail tations in both hardware resources and power supply mean an efficient utilization of hardware resource is of significance. In this paper a novel hardware architecture for Viola and Jones object detectior is proposed. The novel feature of the architecture is Fig. 1. Viola and Jones classifier chain that it features a mechanism of dynamic workload balancing, which adaptively re-distributes the workload among available processing units, thus achieving highly efficient utilization of hardware resource. The ob