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中文c_pcie_blk_plus_ug341.pdf
LogiCORE™ IP
Endpoint Block Plus v1.6
for PCI Express®
用户指南
UG341 2008 年 3 月 24 日
R
R
Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated
herein, none of the Specification may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in
any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written consent of Xilinx. Any unauthorized use of this Specification may violate copyright laws, trademark laws, the laws of privacy and
publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Specification; nor does Xilinx convey any license under its
patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of
the Specification. Xilinx reserves the right to make changes, at any time, to the Specification as deemed desirable in the sole discretion of
Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made . Xilinx will not
assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection
with the Specification.
THE SPECIFICATION IS PROVIDED AS IS WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION
IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR
ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER
EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE SPECIFICATION, INCLU
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