VerilogHDL-chapter1浅析.ppt

Microelectronic center * VDSM(Very Deep Sub-Micron) EDA After 1997: SoC （System on Chip） Top-Down with Bottom-Up System/Macro-block（IP —Intellectual Property ） design by Top-Down design method Implementation of SoC with IP(Intellectual Property) — Bottom-Up 1.2 Evolution of the methodology for IC Desgin Microelectronic center * Deep submicron technology The minimum feature size in semiconductor technology Sub Micron（SM）- 1 micron Deep Sub Micron（DSM）- 1/2 micron Very Deep Sub Micron（VDSM） - 1/4 micron Challenge： Interconnect delay: rising Power, clock, system reliability Device modeling Design capability Microelectronic center * SoC（System on Chip） CPU DSP Analog IF ROM PCB（System） Print Circuit Board 1.2 Evolution of the methodology for IC Desgin Microelectronic center * SoC （System-on-Chip) :Integrated a system into a single chip under proper technology level Deep submicron technology Including one or more microprocessors, random logic and memories with at least 100,000 gates CPU、DSP、digital circuit、analog circuit、memory etc. 1.2 Evolution of the methodology for IC Desgin Microelectronic center * IP(Intellectual Property) usability reusability - To meet the requirement for TTM(Time To Market), Platform-based design method is by utilizing usable blocks(IP) to integrate an SoC 1.2 Evolution of the methodology for IC Desgin Microelectronic center * Technology: 0.18 mm (C10N) Transfer Rate: 850 Mbit/s Package: P-TQFP-100 Analog Area: 20 % (relative) Digital Area: 80 % (relative) ITR 16-State Viterbi FIR Analog-Frontend (incl. Pads) Design partly with Datapath Generator 1.2 Evolution of the methodology for IC Desgin Microelectronic center * IP（VC—Virtual Component） Soft Core：HDL code that can be synthesized Firm Core：Netlist Hard Core ： GDSⅡ Verification Core ： Behavioral HDL model code that can not be synthesized Only for functional verification 1.2 Evolution of the methodology for IC Desgin Microelectronic center *  VDSM—EDA (Top-Down and Bo