EDA实验代码Verilog.doc

实验一、五人表决器 (1)vote5.v ①方案一 `timescale 1ns / 1ps module vote5( input a,b,c,d,e, output f ); assign f=abc||abd||abe||acd||ace|| ade||bcd||bce||bde||cde; endmodule ②方案二 module vote5(a,b,c,d,e,f); input a,b,c,d,e; output f; reg f; reg[2:0] count1; initial count1=0; always@(a,b,c,d,e) begin count1=a+b+c+d+e; f=count13?0:1; end endmodule (2)test.v module test; reg a; reg b; reg c; reg d; reg e; wire f; vote5 uut ( .a(a), .b(b), .c(c), .d(d), .e(e), .f(f) ); initial begin a = 0; b = 0; c = 0; d = 0; e = 0; #100 a = 1; b = 0; c = 0; d = 0; e = 0; #100 a = 1; b = 1; c = 0; d = 0; e = 0; #100 a = 1; b = 1; c = 1; d = 0; e = 0; #100 a = 1; b = 1; c = 1; d = 1; e = 0; #100 a = 1; b = 1; c = 1; d = 1; e = 1; end endmodule (3)vote5.ucf NET a LOC=P11; NET b LOC=L3; NET c LOC=K3; NET d LOC=B4; NET e LOC=G3; NET f LOC=M5; 实验二、加法器 (1)adder.v module adder(a,b,sum,co); parameter n=4; input [n:0] a,b; output [n:0] sum; output co; assign {co,sum}=a+b; endmodule (2)test.v module test; reg [4:0] a; reg [4:0] b; wire [4:0] sum; wire co; adder uut ( .a(a), .b(b), .sum(sum), .co(co) ); initial begin a = 0; b = 0; #100 a = 3; b = 2; #100 a = 10; b = 8; end endmodule (3) adder.ucf NET a3 LOC=N3; NET a2 LOC=E2; NET a1 LOC=F3; NET a0 LOC=G3; NET b3 LOC=B4; NET b2 LOC=K3; NET b1 LOC=L3; NET b0 LOC=P11; NET co LOC=N5; NET sum3 LOC=P6; NET sum2 LOC=P7; NET sum1 LOC=M11; NET sum0 LOC=M5; 实验三、流水灯 (1)ledflash.v module ledflash( output [7:0] ld, input clk ); reg clk1s; reg[7:0] tmp; reg[31:0] count; assign ld=tmp; initial begin clk1s=0; tmp=8 count=0; end always@(posedge clk) begin count=count+1; if (count= begin count=0; clk1s=~clk1s; end end always@(posedge clk1s) begin if (clk1s==1) tmp={tmp[6:0],tmp[