第六章RTL编写.ppt

第六章 RTL编写指南 Outlines What is RTL RTL Implementation Guide Synthesis Coding Style Optimization with DesignWare What is RTL RTL – Register Transfer Level RTL model (code) describe the functionality of the design and is synthesizable to produce the structural netlist Commonly used HDL for RTL code Verilog is more widely used in North America VHDL is more widely used in Europe History of Verilog 1981 Gateway Design Automation released GHDL 1983 Gateway released Verilog HDL 1985 Gateway released enhanced simulator Verilog-XL 1989 Cadence bought Gateway 1990 Cadence released Verilog to public 1995 Reviewed and adopted as IEEE standard 1364 History of VHDL 1970 and 1980 A product of VHSIC program funded by the Department of Defense 1987 First approved as IEEE 1076 standard 1993 Updated to IEEE 1164 standard Outlines What is RTL RTL Implementation Guide Synthesis Coding Style Optimization with DesignWare RTL Implementation Guide Pre-RTL Preparation Checklist RTL Coding Style RTL Structural Considerations RTL Designed for Test RTL for Design Reuse Do not rush for coding unless you have a clear answer: Do you have a detailed specification for your design? Does the spec define how the design is to be partitioned and how the signals are named? Work from the outside-in: what are the I/O requirements? How are the buses defined? Bi-directional or unidirectional? What about the clocks in the design? Testability: Full scan no scan? What other IP are you using? Are there any latency/backward compatibility requirements? Is it your expectation that you are pin-limited or gate limited? Is it your expectation that you will be pushing the speed envelope of the technology? Communication with other team members is necessary Naming convention Clock DFT strategy at block level and top level Etc…… RTL Coding Style Why Coding Style? Making the code more readable, reusable, maintainable Assuring compatibility with most synthesis tools. Bad coding styles can cause mismatches between RTL a