VHDL习题6作业.doc

VHDL第六章课后作业6.1-6.5（2013/12/9） 6.1用if语句描述4选1数据选择器 VHDL描述如下： library ieee; use ieee.std_logic_1164.all; entity mux4_1 is port(d0,d1,d2,d3:in bit; sel : in std_logic_vector(1 downto 0); y : out bit); end mux4_1; architecture one of mux4_1 is begin process(sel,d0,d1,d2,d3) begin if sel=00 then y=d0; elsif sel=01 then y=d1; elsif sel=10 then y=d2; else y=d3; end if; end process; end one; 6.2用IF语句描述四舍五入电路的功能，假定输入的是一位BCD码。 VHDL程序描述如下： Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity sim4_5 is Port( data : in std_logic_vector(3 downto 0); En : in bit; Qout : out std_logic_vector(3 downto 0)); End sim4_5; Architecture one of sim4_5 is Begin Process(en , data) Variable temp : std_logic_vector(3 downto 0); Begin if en=’0’ then qout =’Z’; else temp : =data; end if; if (temp5) then qout =”0000”; else qout =temp+1; end if; end process; end one; 6.3用CASE语句描述七段显示译码器，假定输入的是一位BCD码。 VHDL描述如下（共阴极数码管）： Library ieee; Use ieee.std_logic_1164.all; Entity seg_bcd7 is Port(data : in std_logic_vector(3 downto 0); a,b,c,d,e,f,g : out std_logic); end entity seg_bcd7; architecture one of seg_bcd7 is signal dout ：std_logic_vector(6 downto 0); begin dout= a b c d e f g; process(data,dout) begin case data is when “0000” =dout=”1111110”; when “0001” =dout=”0110000”; when “0010” =dout=”1101101”; when “0011” =dout=”1111001”; when “0100” =dout=”0110011”; when “0101” =dout=”1011011”; when “0110” =dout=”1011111”; when “0111” =dout=”1110000”; when “1000” =dout=”1111111”; when “1001” =dout=”1111011”; when others =dout=”0000000”; end case; end process; end one; 6.4用CASE语句描述4选1数据选择器功能。 VHDL描述4选1数据选择器如下： Librar