DSMDesignandVerificationFlow.ppt

DSM Design and Verification Flow Lecture 21 Alessandra Nardi Outline Conventional design flow review Emerging problems Emerging design flow Design methodology challenges Signal Integrity Reliability Manufacturability Power Conventional Design Flow Verification at different levels of abstraction Verification Techniques Simulation (functional and timing) Behavioral RTL Gate-level (pre-layout and post-layout) Switch-level Transistor-level Formal Verification (functional) Static Timing Analysis (timing) Classification of Simulators Conventional Design Flow Emerging challenges Wire load model Synthesis flow involves the use of statistical wire-load models: Wire load models available in the library are a statistical average based on several previous designs Wire length is a function of the fanout: far from accurate given that fanout are largely design specific Long and painful to achieve timing convergence between pre-layout and post-layout Emerging challenges Wire load model The problem of timing convergence can be addressed by using wire-load models specific to the design (aka custom wire-load models) Custom wire-load model can be obtained by parasitic estimation: Perform initial placement Generate estimated loads Use these to generate custom models Notice that parasitic estimation is not based on actual routing data (as in the case of parasitic extraction) Emerging challengesFloorplan, PlaceRoute Need to achieve timing convergence with minimal number of iterations Routing in general is an extremely computationally expensive task Delays are increasingly dominated by interconnects Transition to a timing-driven placement and route approach Router must adhere to signal integrity, electromigration, power and other such specifications Emerging challengesParasitic Extraction As design get larger, and process geometries smaller than 0.35mm, the impact of wire resistance, capacitance and inductance (aka parasitics) becomes significant Need to model them Parasitic e