NetworksontoMulti-Processor.PDF

Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thiele Abstract Applications based on the Kahn process network (KPN) model of com- putation are determinate, modular, and based on FIFO communication for inter- process communication. While these properties allow KPN applications to effi- ciently execute on multi-processor systems-on-chip (MPSoC), they also enable the automation of the design process. This chapter focuses on the second aspect and gives an overview of methods for automating the design process of KPN applica- tions implemented on MPSoCs. Whereas previous chapters mainly introduced tech- niques that apply to restricted classes of process networks, this overview will be dealing with general Kahn process networks. 1 Introduction Multi-processor system-on-chip (MPSoC) is one of the most promising and solid paradigm for implementing embedded systems for signal processing in communi- cation, medical, and multi-media applications. MPSoC platforms are heterogeneous by nature as they use multiple computation, communication, memory, and periph- eral resources. They allow the parallel execution of (multiple) applications and, at the same time, they offer the flexibility to optimize performance, energy consump- tion, or cost of the system. Nevertheless, to optimize an MPSoC in the presence of tight time-to-market and budget constraints, a systematic design flow is required. To deal with this challenge, Kienhuis et al. [1] suggested to structure the design flow in a certain manner, now commonly referred to as the Y-chart approach. It is a systematic methodology for selecting an embedded system implementation from a set of alternatives, a process often denoted as design space exploration. One key idea underlying this approach is to explicitly separate application and architecture Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thie