VHDL设计FPGA数字系统：计算器课案.docx

PAGE 1 大连海事大学 ┊┊┊┊┊┊┊装┊┊┊┊┊┊┊订┊┊┊┊┊┊┊线┊┊┊┊┊ 毕 业 论 文 二○一四年六月  VHDL设计FPGA数字系统：计算器 专业班级: 通信工程10-3班 姓 名: 马哈得 指导老师: 严 飞 信息科学技术学院  PAGE \* MERGEFORMAT 2  PAGE \* MERGEFORMAT V  PAGE \* MERGEFORMAT I 摘要 本文针对FPGA的计算器数字系统的设计，进行了软件硬件的仿真与实现。实现了计算器控制系统的最基本的加减法功能设计。 本设计所研究的数字系统是由四个不同的模块完成的，包括键盘输入模块、译码模块、计算主控制模块以及数码管显示模块。当键盘输入信号时，依次通过这几个模块，完成数据的运算及显示。其中计算主控制模块完成加减运算，是系统核心模块。 本设计利用EDA技术，用VHDL语言来编程实现四个模块的基本功能，在Quartus II软件中实现模块的设计、编译、综合、优化、仿真直至生成器件之后下载到 FPGA目标芯片上。在ZY11EDA13BE实验系统中完成计算器控制系统的功能的实现，通过键盘等操作输入数值、运算符号，通过数码管及指示灯显示系统运行结果，从而可以更清晰的观察了计算器的运行情况。 关键词：计算器；EDA；FPGA；QuartusII ABSTRACT This article for FPGA of the calculator digital system design, conducted a software hardware Simulation and Realization. A calculator to achieve the control system the most basic functions designs. This design studied Digital System is composed of added and subtracted of module to complete, including the keyboard input module, decoding module, calculate the main control module and a digital tube display module. When the keyboard input signal passes through these modules, complete data display computing requirements. This calculation control system Math four computing module is the core. This design, with the aid of VHDL language to the programming four modules of the basic functions, is in Quartus II software realize the connection and function modules simulation, comprehensive optimization generation device until after the download to FPGA target chip. In the ZY11EDA13BE experimental system mid complete the calculator control function of the system the realization of, through the keyboard, etc. operation input numerical value, computing symbols, through the digital pipe and indicator shows the operation of the system, and a clear view of the operation. Keywords: Calculator; EDA; FPGA; QuartusII; 目录  TOC \o 1-3 \h \z \u HYPERLINK \l _Toc390697470第一章绪论  PAGEREF _Toc390697470 \h 错误！未定义书签。1HYPERLINK \l _Toc390697470第一章绪论 1