清华大学 数字集成系统课件 第九讲Quartus.pdf

Designing with Quartus II Designing with Quartus II Copyright © 2005 Altera Corporation Objectives Objectives Create a New Quartus II Project Compile a Design into an FPGA Perform Timing Analysis Obtain Results Configure an FPGA Create Simulation Waveform Simulate a Design Copyright © 2005 Altera Corporation 2 Altera Programmable Solutions Altera Programmable Solutions Devices Devices (continued) − Stratix® II™ − MAX® II − Cyclone™ II − Mercury™ Devices − Stratix GX − ACEX® Devices − Stratix − FLEX® Devices − Cyclone − MAX Devices Intellectual Property (IP) Tools − Quartus® II Software − Signal Processing − SOPC Builder − Communications − DSP Builder − Embedded Processors Nios® II, Nios − Nios II IDE Copyright © 2005 Altera Corporation 3 Quartus II Development System Quartus II Development System Fully-Integrated Design Tool −Multiple Design Entry Methods −Logic Synthesis −Place Route −Simulation −Timing Power Analysis −Device Programming Copyright © 2005 Altera Corporation More Features More Features −MegaWizard® SOPC Builder Design Tools −LogicLock™ Optimization Tool −PowerPlay Power Analyzer Tool −NativeLink® 3rd-Party EDA Tool Integration −Debug Tools SignalTap® II SignalProbe™ In-System Memory Content Editor −Windows, Solaris, HPUX, Linux Support Copyright © 2005 Altera Corp