SUN小型机介绍.ppt

* * * N2 is housed on a m/board common to both Huron 1U Maramba Using FBDIMM memory – supports dedicated northbound and southbound lanes to and from cache to accelerate perf. Original board layout was with DDR2, but switched to FBDIMM – reality is that b/width is more than ever needed !(no penalty for this, but this is the reason why N2 mem b/width is higher than VF) 42GB/s read and 21GB/s write bandwidth Doubled number of threads per core, now up to 8, also doubled cache banks for 4 to 8 – these give biggest perf boost. Cores now fed by 8 stage pipeline Cores connected to caches and I/O via new crossbar supporting circa 300GB/s bandwidth (up from 135 on N1) FPU unit per core – rather than shared per chip. Fully pipelined, so dramatic acceleration in perf 2 x 10GbE ports direct on chip – connect via ind std XAUI interface – accessed via optional card. Eliminated JBUS – now PCI-E straight into chip at 2.5GHz Over 10 security ciphers supported, operating at wire speed. Most important is AES – std being demanded by NSA. Embedding ciphers allows end to end encryption with no penalty in perf or cost * * * ** * * Application Sparc T3 Series Database B6000 M-Series OS Access SAN Infrastructure / Software / Media / Options EXADATA T52XX Series X4800 X4470 X2270 M2 X4270 M2 X4170 M2 Netra X4200 M2 Netra X4250 Netra X4270 Netra CT900 Netra B6000 Sun 6780/6580/6180 Fiber Channel Arrays Sun FlashStorage Sun ZFS 7720/7420/7320/7120 Unified Storage Sun Storage Tek Tape Lib SPARC 芯片的发展历史 T-Series 1-4 Socket + 2x Throughput M-Series 1-64 Socket + 20% M-Series 8-64 Sockets +6x Throughput +1.5x Single Strand T-Series 1-4 Sockets +3x Single Strand M-Series 8-64 Sockets +2x Throughput T-Series 1-8 Sockets +3x Throughput SPARC 1-64 Sockets +2x Throughput +1.5x Single Strand 5 Year 规划 核数 4x 线程数 32x 内存容量 16x 数据库处理能力 40x Java 每秒处理能力 10x 2010 2011 2012 2013 2014 2015 Solaris 10 Update Solaris 11 Update Solaris 11 Solaris 11 Update Solaris 11 Update SPARC