VHDL语句总结.pptVIP

2、可综合性 同步电路设计规则 1.2 运算符 1.3 顺序语句 If , case和loop语句的综合总结 * * VHDL设计总结 1、顺序语句 信号和变量赋值语句 if 语句 case语句 循环语句（loop） wait 语句 子程序调用语句 return, Null,exit,next等 2、 并行语句 信号赋值语句 条件信号赋值语句 选择信号赋值语句 生成语句 进程语句 块语句 元件例化语句 过程调用语句 library ieee; use ieee.std_logic_1164.all ; entity ex1 is port (din: in std_logic_vector (2 downto 0); dout: out std_logic_vector (3 downto 0)); end ex1 ; architecture rtl of ex1 is begin case (din) is when “00” = dout =“0001” ; when “01” = dout = “0010” ; when “10” = dout =“0100” ; when “11” = dout =“1000” ; end case; end rtl ; 1、易犯的几个典型错误 library ieee; use ieee.std_logic_1164.all; entity ex2 is port ( A,B,C,D: in std_logic; sel: in std_logic_vector(1 downto 0); Z: out std_logic); End ex2; Architecture arch of ex2 is Begin Process(A,B,C,D) Begin Z = A when sel = “00” else B when sel = “01” else C when sel= “10” else D; End process; End arch; library ieee; use ieee.std_logic_1164.all ; entity ex3 is port (clk,d: in std_logic; q: out std_logic); End ex3; Architecture arch of ex3 is Begin Process(clk) Begin Wait until clk’event and clk = ‘1’ ; q = d ; End process; End arch ; library ieee; use ieee.std_logic_1164.all; entity ex4 is port(clk: in std_logic; count: out std_logic_vector(3 downto 0)); end ex4; architecture rtl of ex4 is begin process(clk) begin if clk’event and clk=’1’ then count=count+1; end if; end process; end rtl; Library ieee; use ieee.std_logic_1164.all; Entity ex5 is port(a ,b , enable_a,enable_b: in std_logic ; sig: out std_logic); End ex5; Architechture arch of ex5 is begin a_out = a when enable_a else ‘Z’ ; b_out = b when enable_b else ‘Z’ ; process ( a_out) begin sig = a_out ; end process ; process ( b_out ) beg