AT24C128N-10SU-1.8;AT24C128N-10SU-2.7;AT24C256-10TU-1.8;中文规格书,Datasheet资料.pdf

Features • Low-voltage and Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V) • Internally Organized 16,384 x 8 and 32,768 x 8 • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • 64-byte Page Write Mode (Partial Page Writes Allowed) • Self-timed Write Cycle (5 ms Max) Two-wire Serial • High Reliability – Endurance: One Million Write Cycles – Data Retention: 40 Years EEPROMs • Extended Temperature and Lead-free/Halogen-free Devices Available 128K (16,384 x 8) • 8-lead JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, 8-lead SAP and 8-ball dBGA2 Packages 256K (32,768 x 8) • Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers Description AT24C128(1) The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 AT24C256(2) bits each. The device’s cascadable feature allows up to 4 devices to share a common Two-wire bus. The device is optimized for use in many industrial and commercial appli- Notes: 1. Not recommended for cations where low power and low voltage operation are essential. The devices are new design; please available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC,