THC63LVD104C_Rev.2.1_E - 副本.pdf

THC63LVD104C_Rev.2.1_E THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C receiver is designed to support • Wide dot clock range: 8-112MHz suited for NTSC, pixel data transmission between Host and Flat Panel VGA, SVGA, XGA, and SXGA Display from NTSC up to SXGA resolutions. The • PLL requires no external components THC63LVD104C converts the LVDS data streams back • 50% output clock duty cycle into 35bits of CMOS/TTL data with the choice of the • TTL clock edge programmable rising edge or falling edge clock for the convenience with a variety of LCD panel controllers.At a transmit • Power down mode clock frequency of 112MHz, 30bits of RGB data and • Low power single 3.3V CMOS design 5 b i t s o f t i m i n g a n d c o n t r o l d a t a ( H S Y N C , • 64pin TQFP VSYNC,DE,CNTL1,CNTL2) are transmitted at an • Backward compatible with THC63LVDF64x effective rate of 784Mbps per LVDS channel.Using a (18bits) / F84x(24bits) 112MHz clock, the data throughput is 490Mbytes per second. • Pin compatible with THC63LVD104A • Fail-safe for Open LVDS Input Block Diagram LVDS INPUT CMOS/TTL OUTPUT RA+/- 7 RA6-RA0 L E 7 RB+/- L RB6-RB0 L