【SoCVista】LEON3 V8 SPARC Data Manual.pdf

SPARC V8 32-bit Processor LEON3 / LEON3-FT CompanionCore Data Sheet Features Description • SPARC V8 integer unit with 7-stage pipeline The LEON3 is a 32-bit processor based on the • Hardware multiply, divide and MAC units SPARC V8 architecture. It implements a 7-stage • Separate instruction and data caches pipeline and separate instruction and data caches (Harvard architecture). The number of register • Support for 2 - 32 register windows windows is configurable within the limit of the • Radix-2 divider (non-restoring) SPARC standard. A unique debug interface • Single-vector trapping for reduced code size allows non-intrusive hardware debugging and • Advanced debug support unit provides access to all registers and memory. • Optional IEEE-STD-754 compliant FPU • 25 DMIPS at 25 MHz system clock • Fault-tolerant version available • Support for Fusion, IGLOO, ProASIC3/E, Axcelerator and RTAX-S Product Families 3-Port Register File IEEE-754 FPU Trace Buffer LEON3 Co-Processor 7-Stage Debug port Debug support unit Integer Pipe