目标参考设计缩短了连接功能的实现时间白皮书-Accelerating.PDF

目标参考设计缩短了连接功能的实现时间白皮书-Accelerating.PDF

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目标参考设计缩短了连接功能的实现时间白皮书-Accelerating

White Paper: Spartan-6 and Virtex-6 FPGAs WP359 (v1.0) December 8, 2009 Accelerating System Designs Requiring High-Bandwidth Connectivity with Targeted Reference Designs By: Navneet Rao FPGAs that provide multi-gigabit serial transceivers to implement high-speed serial protocols have become the platform of choice for a large and growing number of applications today. The flexibility to accommodate different protocols, line rates, and emerging standards has made the multi-gigabit serial transceiver the perfect companion to the flexible reprogrammable logic in FPGAs. However, this flexibility comes at a cost. Designing systems that incorporate high-speed serial I/O is difficult enough. Designing systems that work with multiple protocols and different line rates is even more challenging. To provide a simpler, more accessible solution, Xilinx has created fully-functional, fully-validated, and fully-supported connectivity targeted reference designs introduced in two new kits—the Virtex®-6 FPGA Connectivity Kit (DK-V6-CONN-G) and the Spartan®-6 FPGA Connectivity Kit (DK-S6-CONN-G)—that engineers can

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