EDA课后答案.ppt

习 题 习 题 习 题 library ieee; use ieee.std_logic_1164.all; entity sel4_if is port(s1,s0:in std_logic; a,b,c,d:in std_logic; y:out std_logic); end; architecture behave of sel4_if is begin process(a,b,c,d,s1,s0) begin if(s1=0 and s0=0) then y=a; elsif (s1=0 and s0=1) then y=b; elsif (s1=1 and s0=0) then y=c; else y=d; end if; end process; end; 习 题 library ieee; use ieee.std_logic_1164.all; entity sel4_case is port(s1,s0:in std_logic; a,b,c,d:in std_logic; y:out std_logic); end; architecture behave of sel4_case is signal ss:std_logic_vector(1 downto 0); begin ss=s1s0; process(a,b,c,d,ss) begin case ss is when 00= y=a; when 01= y=b; when 10= y=c; when 11= y=d; when others=null; end case; end process; end; 习 题 习 题 library ieee; use ieee.std_logic_1164.all; entity muxk is port(s1,s0:in std_logic; a1,a2,a3:in std_logic; outy:out std_logic); end; architecture behave of muxk is signal tmp:std_logic; begin process(a2,a3,s0) begin 习 题 case s0 is when 0= tmp=a2; when 1= tmp=a3; when others=null; end case; end process; process(a1,tmp,s1) begin case s0 is when 0= outy=a1; when 1= outy=tmp; when others=null; end case; end process; end; 习 题 习 题 library ieee; use ieee.std_logic_1164.all; entity h_sub is port(x,y:in std_logic; diff,s_out:out std_logic); end h_sub; architecture one of h_sub is begin diff=x xor y; s_out=(not x) and y; end one; 习 题 library ieee; use ieee.std_logic_1164.all; entity or_2 is port(a,b:in std_logic; q:out std_logic); end or_2; architecture one of or_2 is begin q=a or b; end one; 习 题 library ieee; use ieee.std_logic_1164.all; entity f_sub is port(x,y,sub_in:in std_logic; diff,s_out:out std_logic); end f_sub; architecture one of f_sub is component h_sub port(x,y:in std_logic; diff,s_out:out std_logic); end component; 习 题 component or_2 port(a,b:in std_logic; q:out std_logic); end component; signal e,f,g:std_logic; begin h_suber1:h_sub port map(