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An Overview of Cache Optimization Techniques ? and Cache{Aware Numerical Algorithms Markus Kowarschik 1 and Christian Wei 2 1 Lehrstuhl fur Systemsimulation (Informatik 10) Institut fur Informatik Friedrich{Alexander{Universitat Erlangen{Nurn b erg, Germany Markus.Kowarschik@cs.fau.de 2 Lehrstuhl fur Rechnertechnik und Rechnerorganisation (LRR{TUM) Fakultat fur Informatik Technische Universitat Munc hen, Germany Christian.Weiss@ 1 Intro duction In order to mitigate the impact of the growing gap b etween CPU sp eed and main memory p erformance, to days computer architectures implement hierar- chical memory structures. The idea b ehind this approach is to hide b oth the low main memory bandwidth and the latency of main memory accesses which is slow in contrast to the oating{p oint p erformance of the CPUs. Usually, there is a small and exp ensive high sp eed memory sitting on top of the hierarchy which is usually integrated within the pro cessor chip to provide data with low latency and high bandwidth; i.e., the CPU registers. Moving further away from the CPU, the layers of memory successively b ecome larger and slower. The mem- ory comp onents which are lo cated b etween the pro cessor core and main memory are called cache memories or caches. They are intended to contain copies of main memory blo cks to sp eed up accesses to frequently needed data [31, 33]. The next lower level of the memory