半导体Flow.ppt

Si3N4 Wafer SiO2 SiO2 Pad Oxidation Poly-Si P-Implant N-Well As(PTS) N-Well P-Well P-Well P-Well ?-Si ?-Si ?-Si WSi WSi WSi TEOS TEOS TEOS SiN SiN SiN P.R. P.R. P.R. P.R. SiN TEOS SiN TEOS SiN SiN As(PTS) P(CC) BPTEOS BPTEOS P.R. P.R. P.R. P.R. α-Si α-Si TEOS TEOS P.R. P.R. RELACS RELACS TEOS SiN ?-Si WSi P.R. P.R. P.R. P.R. B(PTS) B(CD) B(CC) B(PTS) B(CD) N- N- B(CC) N- As As BF2 BF2 BF2 BF2 TEOS TEOS PR a-Si SiN BPTEOS BPTEOS PR PR a-Si TEOS TEOS PR 1.Lamp Annealing(7400C,N2,30sec) skip will peeling 2.Sputter(SE/Ti/TiN=300±30/500±50/300±30) 3.Lamp Annealing(7400C,N2,30sec) 4.W Deposition(4000±300A) 6.Sputter(Ti/TiN/AlCu/TiN=25/400/4000±200/280A) 1M 5.W Etched-back(stop on TEOS) 7.Photolithography 19 PR Al/Cu 9.PR Removal 8.Al/Cu Etching 1M Circle P/D @ ring type : (改善中) 原因判明: 1M Arc TiN thickness is not enough Action : 1M Arc TiN 230A 400A Page * of 50 PSC Confidential 0.15um 製程 Flow 簡介 Al TiN Bad TiN step coverage due to large AlCu grain PR React with PR or developer and can’t be remove during etching Root Cause and Countermeasure Page * of 50 0.15um 製程 Flow 簡介 ▲ 1T Dry Etch O.E 50% 70% ▲ 1T Ash time 212” 84” ▲ 1T New mask single via pair via 1T W missing : (改善濟) 對策: 1T loop 條件變更 (改善濟) 0.15um 製程 Flow 簡介 PHX Fab AAA Page * of 42 PHX Confidential 0.15um 製程 Flow 的簡介 0.15um 製程 Flow 簡介 0.15um 製程 Flow 簡介 Periphery Cell Sense Amplifier Cell – 儲存電荷 : Storage node / Nmos S/A – 放大器與解碼器 : Nmos/Pmos Periphery – 控制電路 : Nmos/Pmos Pad Oxidation 2.non-doped a-Si Deposition(520oC, 200+-20Ao) 3.CVD-Si3N4 Deposition(750oC, 1200+-50Ao) 6.Si3N4 Dry Etching(RIE) 1F a-Si Si3N4 5.Photolithography 1 PR 7.PR Removal(ASH) 8.Trench Etching(-3000Ao,Si3N4 Mask) Wafer 9.Trench Inner Wall Oxidation(11000C, 90min, 254+-22Ao, O2) 10.HDP-CVD P-SiO2 Fill(5200+-300Ao) 11.SiO2 Sintering(11000C,Ar) 4. Plasma ARC Deposition(480+-30Ao) PR SiO2 SiO2 0.15um 製程 Flow 簡介 1.Pad Oxidation(820oC, 170+-8Ao) 1I