ArriaII器件手册卷1第5章：ArriaII器件中的时钟网络与PLL-Altera.PDF

5. Arria II 器件中的时钟网络与 PLL 6? 2011? AIIGX51005-4.1 AIIGX51005-4.1 ® 本章节介绍了 Arria II 器件中具有高级特性的层次时钟网络与锁相环 (PLL)， Arria II 器件提供了专用全局时钟网络 (GCLK)、局域时钟网络 (RCLK) 以及外围时钟 网络 (PCLK)。此外，本章节也涵盖了实时重配置 PLL 计数器时钟频率和相移的详尽说 明，使您能够扫描 PLL 输出频率并动态调整输出时钟相移。 本章节包含以下两方面内容： ■ “Arria II 器件中的时钟网络 ” 第 5–1 页 ■ “Arria II 器件中的 PLL” 第 5–21 页 Arria II 器件中的时钟网络 Arria II 器件中的 GCLK、RCLK 和 PCLK 组成了具有层次结构的时钟架构，此结构提供 了多达 192 个单一的时钟域 (16 GCLK + 88 RCLK + 88 PCLK)，并支持每个器件象限中 多达 60 个单一的 GCLK、RCLK 和 PCLK 时钟源 (16 GCLK + 22 RCLK + 22 PCLK)。 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its ISO semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and 9001:2008 services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Arria II 器件手册 卷 1：器件接口与集成 2011 年 6 月