微电子专业外语7.ppt

Basic MOS Device Physics (2) Depletion capacitance between the channel and the substrate; (3) Capacitance due to the overlap of the gate poly with the source and drain areas, C3 and C4. Design of Analog COMS Integrated Circuit Basic MOS Device Physics Owing to fringing electric field lines, C3 and C4 cannot be simply written as W*LD*Cox, and are usually obtained by more elaborate calculations. 注意： fringing, elaborate Design of Analog COMS Integrated Circuit fringing, elaborate fringe [英] [frind?][美] [fr?nd?] n.穗；边缘；刘海；次要 vt.作为……的边缘， 围绕着；给……加穗饰 adj.边缘的，外围的；次要的，附加的 elaborate [英] [i?l?b?reit][美] [??l?b?ret] vi.详尽说明；变得复杂 Design of Analog COMS Integrated Circuit Basic MOS Device Physics The overlap capacitance per unit width is denoted by Cov; (4) Junction capacitance between the source/drain areas and the substrate. Design of Analog COMS Integrated Circuit Basic MOS Device Physics As shown in Fig. 2.31 (b), this capacitance is usually decomposed into two components: bottom-plate capacitance associated with the bottom of the junction, Cj, and sidewall capacitance due to the perimeter of the junction, Cjsw. 注意: decompose, perimeter Design of Analog COMS Integrated Circuit decompose, perimeter decompose vt. vi. 分解； （使）腐烂 compose vt. 组成，构成； 调解； [印刷]排（字）； 使安定 Perimeter [英] [p??r?m?t?] [美] [p??r?m?t?] n. 数周长； 周围，边界 Design of Analog COMS Integrated Circuit Basic MOS Device Physics The distinction is necessary because different transistor geometries yield different area and perimeter values for the S/D junctions. 注意： distinction, geometries Design of Analog COMS Integrated Circuit distinction, geometries distinction [英] [dis?ti?k??n][美] [d??st??k??n] n.区别；荣誉；特质；卓越 geometry [英] [d?i??mitri][美] [d?i?ɑm?tri] n.几何学；几何形状；几何图形；几何学著作 Design of Analog COMS Integrated Circuit Basic MOS Device Physics We typically specify Cj and Cjsw as capacitance per unit area and unit length, respectively. 注意： respectively Design of Analog COMS Integrated Circuit Basic MOS D