32位嵌入式CPU中系统控制协处理器的设计(国外英语资料).doc

32位嵌入式CPU中系统控制协处理器的设计(国外英语资料) Design of system control coprocessor in 32 bit embedded CPU Abstract: system control coprocessor is one of the necessary modules in MIPS architecture CPU. Its main function is to use a series of privileged registers to record the current state of the CPU, to handle exception / interrupt, and to provide the environment required for the normal execution of the instruction. This paper discusses the design of a system control coprocessor in MIPS 4Kc instruction set CPU, including the operation of privilege register writing, the accurate exception handling mechanism and the fully custom back end physical design. Keywords: system control coprocessor; precise exception handling; pipelining; full customization MIPS system control coprocessor in CP0, it provides the necessary instructions of normal execution environment, the exception / interrupt handling, cache fill, virtual address conversion, operation mode of operation. From a hardware point of view, the system control coprocessor acts on the instruction set as much as the operating system does to the application. exception handling CPU often needs to interrupt the normal execution of the instruction process, jump to execute a particular instruction segment, and then restore the original instruction sequence. The MIPS architecture calls such a process an exception (Exception). All exceptions are handled with a unified mechanism. For the exception, the following 3 measures need to be taken: 1) anomaly detection: CPU to detect which part of what happened in general, anomaly; anomaly detection by each module, such as adding overflow by the adder in the process of operation, and in the water section of the corresponding is system control coprocessor CP0 read. Therefore, this part of the function does not fall within the scope of CP0s design. 2) exception handling: CPU according to the priority which the exception is handled, and the context switches necessary (Context Switch), to prepare for th