A 0.9V 0.35μm Adaptively Biased CMOS LDO.pdf

Please click on paper title to view Visual Supplement. ISSCC 2008 / SESSION 24 / ANALOG POWER TECHNIQUES / 24.5 24.5 A 0.9V 0.35µm Adaptively Biased CMOS LDO nant pole generated at VEA tracks with the GBW and the regulator Regulator with Fast Transient Response remains stable as IOUT varies. Yat-Hei Lam, Wing-Hung Ki Figure 24.5.2 shows a conventional current mirror CM and the SCM. The CM achieves a high current gain by using a large tran- Hong Kong University of Science and Technology, Kowloon, China sistor aspect ratio. Speed is limited by the large time constant of C /g where g is the transconductance of the diode-connected g mIN, mIN Portable applications often need multiple voltages controlled by a input transistor MIN, and Cg is the total equivalent gate capaci- power management IC to power up many functional blocks [1]. A tance of both MIN and MOUT. The proposed SCM utilizes a low-volt- switching pre-regulator is usually followed by a low dropout (LDO) age transient-enhancing circuit that provides extra transient cur- regulator to provide a regulated power source for noise-sensitive rent to Cg to enhance the current mirroring speed. A very small on- blocks. The LDO regulator has to be stable for all load conditions chip compensation resistor, RZ = 250Ω, is sufficient to stabilize the and frequency compensation is usually needed to stabi