阵列+ 可编程输出电路.PPT

EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * * Winter 2009 ZDMC – Lec. #09 3. 互连资源 * Winter 2009 ZDMC – Lec. #09 Xilinx 4000 Interconnect * Winter 2009 ZDMC – Lec. #09 Xilinx FPGAs (interconnect detail) * Winter 2009 ZDMC – Lec. #09 4. SRAM分布式每一位触发器控制一个编程点 * Winter 2009 ZDMC – Lec. #09 Details of Virtex-E Slice LUT 4-input fun 16x1 sram 32x1 or 16x2 in slice 16 bit shift register Storage element D flipflip latch Combinational outputs 5 and 6 input functions Carry chain arithmetic along row or col * Winter 2009 ZDMC – Lec. #09 二、编程数据的装载 数据可先放在EPROM或PC机中 通电后，自行启动FPGA内部的一个时序控制逻辑电路，将在EPROM中存放的数据读入FPGA的SRAM中 “装载”结束后，进入编程设定的工作状态 ！！每次停电后，SRAM中数据消失 下次工作仍需重新装载 * Winter 2009 ZDMC – Lec. #09 Xilinx FPGA Adder Example Example 2-bit binary adder - inputs: A1, A0, B1, B0, CIN  outputs: S0, S1, Cout Full Adder, 4 CLB delays to final carry out 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out FPGA architecture * Winter 2009 ZDMC – Lec. #09 * Winter 2009 ZDMC – Lec. #09 Virtex-E Family of Parts * Winter 2009 ZDMC – Lec. #09 Why are FPGAs Interesting? Technical viewpoint: For hardware/system-designers, like ASICs only better! “Tape-out” new design every few minutes/hours. Does the “reconfigurability” or “reprogrammability” offer other advantages over fixed logic? Dynamic reconfiguration? In-field reprogramming? Selfmodifying hardware,evolvable hardware? FPGAs have tracked Moore’s Law better than any other programmable device. Staggering logic capacity growth (10000x): * Winter 2009 ZDMC – Lec. #09 Why are FPGAs Interesting? Logic capacity now only part of the story: on-chip RAM, high-speed I/Os, “hard” function blocks, ... Modern FPGAs are “reconfigurable systems” Have been an archetype for the semiconductor