(内存基本知识)4DRAM工作原理.pptVIP

* * In this example, we are showing a six-transistor circuit. The basic storage element of SRAM is a 6-transistor circuit provided by cross-coupled inverters. This configuration will Hold a 1 or 0 as long as the system continues to receiver power. Addressing is simple. * High capacity is due to an extremely efficient memory element. DRAM cell consist of a single access transistor and a capacitor. More complicated addressing scheme. * Refresh means the memory elements must be read and written back to their storage location. Since we need a refresh cycle, an external memory controller is needed to keep track of the last row to be refreshed. To simplify the memory controller design, some DRAMs have a refresh row pointer in the memory chip. A special CAS before RAS signaling convention implements the refresh. If CAS goes low before RAS, the chip recognizes this as a refresh cycle. The indicated row is read, written back, and the internal indicator points to the next row to be refreshed. Activating a Row Activating a Row Must be done before a read or write Just latch the row address and turn on a single wordline Writing Writing A row must be active Select the column address Drive the data through the column mux Stores the charge on a single capacitor Reading Reading A row must be active Select the column address The value in the sense-amplifier is driven back out The Sense-Amplifier Sense-Amplifier A pair of cross-coupled inverters Basically an SRAM element Weaker than the column mux Write data will “outmuscle” the sense-amplifier Keeps the data at full level Precharge Precharge Inactive state (no wordlines active) Precharge control line high Ties the two sides of the sense-amp together This makes the bitlines stay at VDD/2 Only stable as long as the precharge control line is high—otherwise this is unstable! No capacitors connected Activation Revisited Activation Turn off the precharge control line Makes the sense-amp unstable—it wants to go to either 0