北科自动化数电pp6.ppt

CHAPTER 6 Functions of Combinational Logic In this chapter you should know: The internal functional principle of every MSI chips (in brief) Those MSI chips are combinational circuit (that means they are composed of logic gates); you should learn how to use them Focus on these two blocks named decoder and data selector which can be used to produce some given logic function 6-1 Basic Adders(implementing 1-bit addition)  基本加法器 6-1-1 Half-Adder(半加器) 6-1-2 Full-Adder 全加器 6-1-3 Full adder from two half-adder circuits 6-2 Parallel Binary Adders(implementing more-bit addition)并行二进制加法器 6-2-1 Two-bit parallel binary adder 6-2-2 Four-bit parallel binary adder 四位并行二进制加法器 ripple carry（串行进位） adder showing “worst-case” carry propagation delays. Another application of adder:A voting system 6-3 Comparators 数值比较器 Pin diagram and logic symbol for the 74HC85 4-bit magnitude comparator. 6-5 Encoders 编码器 Example: 用两片74LS148接成16线－4线优先编码器 Logic symbol for a decimal-to-BCD encoder. Pin diagram and logic symbol for the 74HC147 decimal-to-BCD priority encoder (HPRI means highest value input has priority). Application: A simplified keyboard encoder. Assignments: (due to next Monday) P232 6、8、12 补充作业题： 用4片74LS148组成32线－5线优先编码器，允许附加必要的门电路。 6-4 Decoders 译码器 6-4-1 Binary decoder（二进制译码器） 6-4-2 BCD-to-decimal decoder （BCD码-十进制译码器） 6-4-3 BCD-to-7-segement decoder （BCD码-七段显示驱动译码器） Binary inputs Active-low outputs 例：用两片74LS138接成4线－16线译码器 6-4-2 BCD-to-decimal decoder 6-8 Multiplexers (Data Selectors) 多路复用器/数据选择器（MUX） A MUX is a device that allows digital information from several sources to be routed onto a single line for transmission over that line to a common destination. The basic multiplexer has several data-input lines and a single output line. 4-input multiplexer Waveform 双4选1数据选择器74LS153 Pin diagram and logic symbol for the 74LS151 8-input data selector/multiplexer. Ex 6-17: Data selector/multiplexer connected as a 4-varia