复习课lyn.ppt

EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * For lecture Evaluate transistor, Me, eliminates static power consumption EE141 * CL being lower also contributes to power savings EE141 * CL being lower also contributes to power savings EE141 * EE141 * EE141 * EE141 * EE141 * One and only one of the networks (PUN or PDN) is conducting in steady state EE141 * One and only one of the networks (PUN or PDN) is conducting in steady state EE141 * Shown synthesis of pull up from pull down structure EE141 * EE141 * Note capacitance on the internal node – due to the source grain of the two fets in series and the overlap gate capacitances of the two fets in series EE141 * EE141 * Assumes Rp = Rn EE141 * For class lecture. Red sizing assuming Rp = Rn Follow short path first; note PMOS for C and B 4 rather than 3 – average in pull-up chain of three – (4+4+2)/3 = 3 Also note structure of pull-up and pull-down to minimize diffusion cap at output (e.g., single PMOS drain connected to output) Green for symmetric response and for performance (where Rn = 3 Rp) Sizing rules of thumb PMOS = 3 * NMOS 1 in series = 1 2 in series = 2 3 in series = 3 etc. EE141 * While output capacitance makes full swing transition (from VDD to 0), internal nodes only transition from VDD-VTn to GND C1, C2, C3 on the order of 0.85 fF for W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS CL of 3.2 fF with no output load (all diffusion capacitance – intrinsic capacitance of the gate itself). To give a 80.3 psec tpHL (simulated as 86 psec) EE141 * M1 have to carry the discharge current from M2, M3, … MN and CL so make it the largest MN only has to discharge the current from MN (no internal capacitances) EE141 * For lecture. Critical input is latest arriving signal Place latest arriving signal (critical path) closest to the output EE141 * Reduced fan-in - deeper logic depth Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate (second configuratio