第五章 状态机.ppt

PROCESS REG 时序进程 PROCESS COM 组合进程 PROCESS LATCH 锁存器 current_state next_state LOCK 状态机FSM FPGA/CPLD CLK CS A0 RC K12/8 STATUS D[11..0] AD574 Q[11..0] 模拟信号输入 采样数据输出 【例4】AD574三进程采样状态机设计 【例4】AD574三进程采样状态机设计 1时序进程＋1组合进程＋1辅助进程 … … COM: PROCESS(current_state,STATUS) BEGIN –-例3中的两个组合进程合二为一 CASE current_state IS WHEN st0 = next_state = st1; CS = 1; A0 =1; RC=1; LOCK = 0; WHEN st1 = next_state = st2; CS = 0; A0 =0; RC = 0; LOCK = 0; WHEN st2 = IF (STATUS=1) THEN next_state = st2; ELSE next_state = st3; END IF ; CS =0; A0 =0; RC =0; LOCK =0; WHEN st3= next_state = st4; CS =0; A0 =0; RC =1; LOCK =0; WHEN st4 = next_state = st0; CS =0; A0 =0; RC =1; LOCK =1; WHEN OTHERS = next_state = st0; END CASE ; END PROCESS COM ; …… 状态机RTL电路图 【例4】AD574三进程采样状态机设计 状态机工作时序图 状态2：等待 【例4】AD574三进程采样状态机设计 【例5】单（混合主控）进程Moore型状态机 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MOORE1 IS PORT ( DATAIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0); CLK,RST : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END MOORE1; ARCHITECTURE behav OF MOORE1 IS TYPE ST_TYPE IS (ST0, ST1, ST2, ST3,ST4); SIGNAL C_ST : ST_TYPE ; --状态指针 BEGIN PROCESS( CLK,RST ) BEGIN IF RST =1 THEN C_ST = ST0 ; Q = 0000 ; ELSIF CLKEVENT AND CLK=1 THEN 接下页 CASE C_ST IS WHEN ST0 = IF DATAIN =10 THEN C_ST = ST1 ; ELSE C_ST = ST0 ; END IF; Q = 1001 ; WHEN ST1 = IF DATAIN =11 THEN C_ST = ST2 ; ELSE C_ST = ST1 ; END IF;