基于冗余抑制技术的低功耗组合电路设计-电子学报.PDF

5 Vol.30 No. 5 2002 5 ACTA ELECTRONICA SINICA May 2002 1 2 3 吴训威 , 卢仰坚,M Pedram ( 1 , 315211;2 , 310027; 3 , CA 90089) : , ., .PSPICE . : ; ; ; : TP331; TN431 : A : (2002) Design of Low Power Combinational Circuits Based on RedundancyRestraining Technique 1 2 3 W Xunwei ,L Yangjian ,Massoud Medram (1Inst. of Circuits and Systems, Ningbo University, Ningbo, Zhejiang 315211, China; 2Dept. of Inf o. Elect. Eng, Zhejiang University, Hangzhou, Zhejiang 310027, China; 3Dept. of Elect. Eng. Syst, University of Southern Calfi ornia, CA90089, USA) Abstract: The low power design principle based on redundancyrestraining technique is explained in this paper.Various con structions for restraining redundancy in combinational circuits and their working mechanism are analyzed.Furthermore, a low power magnitude comparator design based on this technique is proposed.PSPICE simulation and energy analysis proves that saving energy dissipation can be effectively achieved by using this design technique. Key words: CMOS; low power; redundancyrestraining;magnitude comparator 1 ;(2) CMOS , ( ) . ,, . , , , , ;( 3) . , . , [3] [1] ( Doubleedge triggered flipflops) .