如何提高fpga速度（How to improve fpga speed）.doc

如何提高fpga速度（How to improve fpga speed） For designers, we certainly hope that the frequency of the circuits we design will be as high as possible (in this case, the frequency of work refers to the frequency of work in the FPGA). We also often hear use resources in speed, with flowing water can improve the working frequency, it is a very important method, today I want to further to analyze how to improve the working frequency of the circuit. Lets first analyze what affects the frequency of the circuit. The working frequency of our circuit is mainly related to clock skew when the signal propagation between registers and registers is transmitted. Inside the FPGA, if the clock goes in the long line, the clock skew is very small, and its basically negligible, and for the sake of simplicity, were only thinking about the delay factor in the propagation of the signal. Signal transmission delay including register running switch time delay, time delay, after a delay of combinational logic (division may not be very accurate, but for analyzing problems there should be no possible), to improve the working frequency of the circuit, we will be in the three delay, to make it as small as possible. We first see switch delay, the delay is determined by the device physics, we have no way to change, so we can only by changing the way to get the line and reduce the combinational logic methods to improve the working frequency. 1. Reduce delay by changing the way of walking. Altera devices, for example, we are in the inside of the quartus timing closure floorplan can see there are a lot of all activity, we can all activity according to the row and column points, each bar represents a LAB, each LAB has eight or ten LE. Their walking delay is as follows: in the same LAB (fastest) (as in the same column or peers). Our comprehensive device to add appropriate constraints (not greedy, usually to add 5% margin is more appropriate, such as circuit working at 100 MHZ, then it is ok to add constraints