CMOS集成时钟恢复电路设计.pdf

第29 卷第6 期 电 子 与 信 息 学 报 Vol.29No.6 2007 年6 月 Journal of Electronics Information Technology Jun. .2007 CMOS 集成时钟恢复电路设计 李学初 高清运 陈浩琼 秦世才 (南开大学信息技术科学学院 天津 300071) 摘 要：该文设计了一个集成时钟恢复电路，恢复时钟的频率为 125MHz。通过采用电流相减技术等补偿措施， 很大程度上降低了振荡器的压控增益，从而在不影响电路性能的前提下大大地降低了芯片面积。本设计采用 0.25μm标准CMOS工艺实现，有效芯片面积小于 0.2mm2，功耗仅10mW。在各种工艺角、温度以及供电电源条 件下的仿真结果均表明，该电路相位偏差小于200ps，时钟抖动的峰峰值小于150ps。该文对一个采用本时钟恢复 电路的100MHz PHY系统进行流片、测试，验证了时钟恢复电路能够正常工作。 关键词：时钟恢复；100MHz PHY；Hogge 鉴相器；锁相环 中图分类号：TN432 文献标识码：A 文章编号：1009-5896(2007)06-1496-04 The Design of Monolithic CMOS Clock Recovery Circuit Li Xue-chu Gao Qing-yun Chen Hao-qiong Qin Shi-cai (College of Information Technology and Science, Nankai University, Tianjin 300071, China) Abstract: A monolithic clock recovery circuit is proposed in this paper. The frequency of the recovered clock is 125MHz. By using of some compensation methods, such as current subtraction technology, the gain of the VCO is greatly diminished, as a result the chip area is reduced also without sacrificing the noise performance of the recovered clock. This design is implemented by a 0.25μm standard CMOS technology. The active chip area is less than 0.2mm2 , and the power consumption is only 10mW. The simulation results in different temperature and process condition indicate that the phase error of the recovered clock is less than 200ps and the peak-to-peak jitter is less than 150ps. A 100MHz PHY with the proposed clock recovery circuit inside is taped out and tested. The test result shows that the clock recovery circuit works properly. Key words: Clock recovery; 100MHz PHY; Hogge phase detector; PLL 1 引言 结果表明，当网线在5m到100m范围内变