如何Step by Step实现USB host-我的实战经验（How to implement USB by Step Step host- my actual combat experience）.doc

如何Step by Step实现USB host-我的实战经验（How to implement USB by Step Step host- my actual combat experience） A project was made a few days ago, in which the functions of USB were realized, including the reading and writing of the U disk and the use of USB mouse keyboard. After a period of debugging, it was finally completed. Now a number of key debugging points down, on the one hand about finishing their own ideas, on the other hand, I hope to be able to do something similar to the work of some of the brothers reference, we hope to be helpful. My system is Linux 2.6, USBs main controller uses EPSONs S1R72V17, and USBs drive code is provided by Epson Corp. Before I started, I downloaded the relevant information from EPSONs website, including the datasheet and hardware design documents and the software porting document of this chip. (data download website: http://www.epson.jp/device/semicon_e/product/inteRFace/index.htm) In the process of this project, my main task is to complete the design and debugging of hardware, and to transplant the EPSON Linux 2.6 driver to my system. USB hardware system design is relatively simple (refer to the following figure), through the address data bus and CPU connected, and the other USB controller has an interrupt signal to access the CPU system. S1R72V17 requires 3 different voltages, namely 3.3V, 1.8V, and 5V. Another part of the circuit is the interface circuit of USB, including differential signal line pair and over-current protection circuit. In addition, the 72v17 also needs a clock that can be supplied by 12M crystals, or by active oscillators such as the 24M or 48M. In the design of the hardware circuit, the key is the connection of the bus and the alignment of the differential signal line. 72V17 has 3 bus access mode, respectively is 8bits mode, BE mode and 16bits 16bits strobe model, BE model and WBEH WBEL CPU to provide access to the signal level respectively, byte, strobe mode WRH and CPU provide the WRL signal to access low byte.