High Speed Layout Guidelines TI（高速布局指南 TI）.pdf

Application Report SCAA082 – November 2006 High-Speed Layout Guidelines Alexander Weiler and Alexander Pakosta Clock Drivers ABSTRACT This application report addresses high-speed signals such as clock signals and their routing and gives designers a review of the important coherences. With some simple rules, electromagnetic interference problems can be minimized without using complicated formulas and expensive simulation tools. Section 1 gives a short introduction to theory; section 2 focuses on practical PCB design rules. Either section can be read independently. Contents 1 Theoretical Overview 2 1.1 Electromagnetic Interference and Electromagnetic Compatibility 2 1.2 Clock Signals 2 1.3 Transmission Lines 3 1.4 Crosstalk 8 1.5 Differential Signals 8 1.6 Return Current and Loop Areas 8 2 Practical PCB Design Rules 9 2.1 PCB Considerations During the Circuit Design 9 2.2 Board Stackup 9 2.3 Power and Ground Planes 10