IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. （IEEE固态电路杂志》,卷。）.pdf

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010 565 High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique Mohamed El-Nozahi, Student Member, IEEE, Ahmed Amer, Student Member, IEEE, Joselyn Torres, Student Member, IEEE, Kamran Entesari, Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE Abstract—A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain–bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 m CMOS technology and achieves a PSR better than 56 dB up to Fig. 1. Block diagram of typical power management system. 10 MHz for load currents up to 25 mA. Load regulation of 1.2 mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 A with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves nologies which requires complex gain stages to achieve better such a high PSR up to 10 MHz. regulation, and 3) finite bandwidth of the feedback path. Index Terms—CMOS, DC-DC converters, feed-forward ripple Researchers have contributed to improve power-supply rejec- cancellation, low drop-out regulator, power-supply rejection. tion techniques. Some of those techniques are: i) Using simple