EDA VHDL基本描述语句(第六七八九十一二讲).ppt

;; IF 条件 THEN 语句 ； ELSIF 条件 THEN 语句 ； ELSIF 条件 THEN 语句 ； …… ELSE 语句 ； END IF;;If 的条件必须是布尔表达式！;含多条语句;LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY ddf IS PORT (CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q, QD: OUT STD_LOGIC ); END ddf; ARCHITECTURE ex OF ddf IS BEGIN ;PROCESS (CLK) BEGIN IF (CLKEVENT) AND (CLK = 1‘) THEN Q = D; QD= not D; END IF; END PROCESS ; END ARCHITECTURE ex ;; 【例】用VHDL设计一家用告警系统的控制逻辑，它有来自传感器的三个输入信号smoke、door、water和准备传输到告警设备的三个输出触发信号fire_alarm、burg_alarm、water_alarm以及使能信号en和alarm_en。;PROCESS(smoke,door,water,en,alarm_en) BEGIN  IF ((smoke= ‘1’) AND (en= ‘0’)) THEN  fire_alarm = ‘1’;  ELSE  fire_alarm = ‘0’;  END IF;;例，加热控制器： entity thermostat is port ( desired_temp, actual_temp : in integer; heater_on : out boolean ); end entity thermostat; -------------------------------------------------- architecture example of thermostat is begin controller : process (desired_temp, actual_temp) is begin if actual_temp desired_temp - 2 then heater_on = true; elsif actual_temp desired_temp + 2 then heater_on = false; end if; end process controller; end architecture example;;缅备额涩胚乐届催芝释肯茶妊入豹操找秽杜烃农永窒漱牌灶朔剥驶奢革呈EDA VHDL基本描述语句(第六七八九十一二讲)EDA VHDL基本描述语句(第六七八九十一二讲);;喘犯捎严但腋成筋镣桶豪吁捏匝帚油宦氖烩遗恍拄畦铲赌罪沾汝夯舞删氖EDA VHDL基本描述语句(第六七八九十一二讲)EDA VHDL基本描述语句(第六七八九十一二讲);Case 语句的选择项必须是一个静态值！; PORT(… z1 , z2 , z3 , z4 : out std_logic); … SIGNAL value : INTEGER RANGE 0 TO 15; BEIGIN PROCESS (value) IS BEGIN CASE value IS WHEN 0 = z1 = ‘1’ ; - - value=0时 WHEN 1 | 3 = z2 = ‘0’ ; - - value=1或3时 WHEN 4 TO 7 | 2 = z3 = ‘1’ ; - - value=4、5、6、7或2时 WHEN OTHERS = z4 = ‘1’ ; - - value=8~15时 END CASE; END PROCESS;; SIGNAL value : INTEGER RANGE 0 TO 15; SIGNAL out1 : STD_LOGIC ; ... CASE value IS --