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04_FPGA功耗优化课件
Power Reduction Techniques
Altera Asia Pacific Regional Support Center
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2
Agenda
Introduction
Power-Driven Synthesis
Power-Driven Fitting
Clock Power Management
Low-Power Design
Conclusion
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Introduction
67%
22%
11%
Dynamic Power DominantFocus of Power Optimization
99 Customer Designson Stratix II Devices
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Dynamic Power Optimization Flow
Automatic, but less accurate
Requires testbench,more accurate
Evaluate Power
RTL
Simulation
Power-Driven Fit
Design
Power Report
Vectorless
Estimation
Hardware
Measurement
Gate-Level Simulation
+ Power Analyzer
Estimate Toggle Rates
Normal
or
Extra effort
Power-Driven
Synthesis
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5
Power-Driven Synthesis
Located under: “Analysis Synthesis Settings”
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Power-Driven Synthesis Options
Extra effort
More power reduction
May increase compile time
Normal compilation (Default)
Standard power reduction
No effect on compile time or design performance
Off
No optimization
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Power-Driven Synthesis for RAM
Memory Optimization
Normal compilation Setting
Promote Read/Write Enable Signals to Clock Read/Write Enable Signals
Extra effort Setting
Promote Read/Write Enable Signals to Clock Read/Write Enable Signals
AND Power-Aware Memory Balancing
Memory Balancing configures RAM for optimal need
Default setting selects narrow/deeper memory configurations
e.g. 4 1k x4 blocks (x4=narrow; 1kwords=deeper)
MW “Maximum Depth” option selects wider/shallow RAMs for power
e.g. 4 256 x16 blocks (x16=wider; 256words=shallow)
Access only valid memory slice, disable the rest
Does require additional decoder and mux logic however
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RAM Enable Optimization
Con
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