第六章RTL编写课件.ppt

第六章;Outlines;What is RTL ;History of Verilog;History of VHDL;Outlines;RTL Implementation Guide;Do not rush for coding unless you have a clear answer: Do you have a detailed specification for your design? Does the spec define how the design is to be partitioned and how the signals are named? Work from the outside-in: what are the I/O requirements? How are the buses defined? Bi-directional or unidirectional? What about the clocks in the design?;Testability: Full scan no scan? What other IP are you using? Are there any latency/backward compatibility requirements? Is it your expectation that you are pin-limited or gate limited? Is it your expectation that you will be pushing the speed envelope of the technology? ;Communication with other team members is necessary Naming convention Clock DFT strategy at block level and top level Etc……;RTL Coding Style;General RTL Coding Style ;General RTL Coding Style – cont.;RTL Structural Considerations;RTL Designed for Test;RTL Designed for Test -cont.;RTL for Design Reuse;RTL for Design Reuse - cont.;RTL for Design Reuse - cont.;Outlines;Keep in Mind When You Writing RTL:;Coding vs. Physical Implementation;Register and Latch;Procedure Assignments;Aware of Event List;Partitioning for Physical Implementation;Partitioning for Physical Implementation;Partitioning for Physical Implementation;Partitioning for Physical Implementation; Partitioning for Physical Implementation ;Partitioning for Physical Implementation;Partitioning for Design Reuse;Checking RTL Coding Style;Check Coding with Trial Synthesis ;Outlines;Using Synopsys DesignWare Lib;Categories of DesignWare Lib;Enabling DesignWare License;Using DesignWare Lib in RTL Code;Example of Using DesignWare ;Example of Using DesignWare ;Summary;References;Thank you