0．13μm CMOS下的1000Base—T联合解码均衡器.pdfVIP

第34卷 第1期 计 算 机 工 程 2008年1月 VoL34 No．1 Computer Engineering January 2008 ·工程应用技术与实现· 文章编号#1oo 428(20o8)o1—023 __03 文献标识码。A —q3111~ —：TN47 0．13pm CMOS下的1000Base．T联合解码均衡器 诸 悦，戎蒙恬 (上海交通大学电子信息与电气工程学院电子工程系，上海 200240) 羹 ||}：分析了o．13 1 CMOS工艺下适合于IEEE 802．3 ab标准1000Base—T千兆以太网收发器的联合解码均衡器结构。通过分析适用于 1000 Base—T的超前计算技术，对超前计算结构进行了优化，降低了现有联合解码均衡器在O．13 1工艺下的硬件复杂度。通过物理设计确 定了优化的联合解码均衡器的算法与结构。优化后，14抽头MA4在O．13 gm工艺下门数减少了8．7 k，约9％，14抽头并行判决反馈解码 器门数减少了9．5 k，约6％。 关嘲 ：1000Base—T；千兆以太网；M算法；并行判决反馈解码器；超前计算技术 Joint Trellis Decoder and Equalizer in 0．13pm CMOS Process for 1000Base-T Gigabit Ethernet Transceiver ZHU Yue。RONG Meng．tian (Dept．of Electronic Engineering，School of Electronic Information and Electrical Engineering，Shanghai Jiaotong University,Shanghai 200240) I[AbstractIThis paper analyzes the architecture ofjoint TCM decoder and equalizer which suits for IEEE802．3ab std．．1000Base—T gigabit Ethemet transceiver in 0．13gm CMOS process．Look-ahead technologies available for 1000Base—T are studied tO optimize the look—ahead structures employed in the joint TCM decoder and equalizer．Hardware complexity of the decoder is decreased by those approaches without performance scaled down．8．7k gates of 14t,ap MA4 decoder is saved after optimization．which is about 9％of original circuits．The gate count of 14tap PDFD is decreased by 9．5k．which saves about 6％in area after optimization． [Key wor~sI 1000Base— gigahit Ethernet；M—algorithm；parallel decision feedback decoder；look-ahead technology 1000Base—T千兆以太网…在 4对非屏蔽双绞线上以 1 I翰i§器结构 125 MBaud调制率传送4D—PAM5信号，以达到1 Gb／s的数 对于1000Base—T应用而言，PDFD与MA具有相似的行 据传输率。4D—PAM5信号在提高频谱利用率的同时，其电平 为级结构，如图1所示，其中，ACSU对应于PDFD；A