标准数字工艺下16位精度低压低功耗_模数调制器设计.pdfVIP

第 32 卷第 2 期 电 子 与 信 息 学 报 Vol.32No.2 2010 年 2 月 Journal of Electronics Information Technology Feb. 2010 标准数字工艺下16 位精度低压低功耗ΣΔ模数调制器设计 殷树娟 李翔宇 孙义和 (清华大学信息科学与技术国家实验室 北京 100084) 摘 要：针对输入信号频率在 20 Hz~24 kHz 范围的音频应用，该文采用标准数字工艺设计了一个 1.2 V 电源电压 16 位精度的低压低功耗 ΣΔ模数调制器。在 6 MHz 采样频率下，该调制器信噪比为 102.2 dB，整个电路功耗为 2.46 mW。该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器，在低电源电压情况下实现高摆率高 增益要求的同时不会产生更多功耗。另外，采用高线性度、全互补 MOS 耗尽电容作为采样、积分电容使得整个电 路可以采用标准数字工艺实现，从而提高电路的工艺兼容性、降低电路成本。与近期报道的低压低功耗 ΣΔ模数调 制器相比，该设计具有更高的品质因子 FOM。 关键词：ΣΔ模数调制器；低压；低功耗；开关电容；耗尽电容 中图分类号：TN402 文献标识码：A 文章编号：1009-5896(2010)02-0464-06 DOI: 10.3724/SP.J.1146.2009.00116 Design of 16 bit Low-Voltage Low-Power ΣΔ Modulator with Standard Digital Technology Yin Shu-juan Li Xiang-yu Sun Yi-he (National Laboratory of Information and Technology, Tsinghua University, Beijing 100084, China) Abstract: For audio signals with input frequency between 20 Hz and 24 kHz, a switch-capacitor feed-forward ΣΔ A/D modulator in 0.18μm Logic technology is proposed in this paper, which gains 16 bit resolution with 1.2 V supply voltage. The modulator can achieve 102.2 dB signal-to-noise ratio (SNR) under 6MHz sample clock, and the total power dissipation is only 2.46 mW. In the modulator, a pseudo-two-stage Class-AB transconductance amplifier is used, which has high slew rate and open loop gain while without increasing power dissipation. What is more, full compensated depletion-mode capacitors are used as sample capacitors and integrating capacitors to enable the whole chip to be fabricated in standard digital technology, which is good to reduce chip cost and improve the