chapter3_part2集成电路物理结构.ppt

基本工艺层版图 金属层:与多晶接触 多晶与Metal1的连接 多晶对接触孔的最 小覆盖余量 Metal1与Metal1的 最小间距 多晶接触孔的 最小边长 * * PAD * * 实验所采用的设计规则 * * 实验所采用的设计规则 规则 描述 规则类型 lambda 1.1 Well Minimum Width Min width 10 1.2 Well to Well (Different Potential) Spacing No check 1.3 Well to Well (Same Potential) Spacing Spacing 6 表1：采用的阱（Well）规则 * * 实验所采用的设计规则 表2：有源区（Active）规则 规则 描述 规则类型 lambda 2.1 Active Minimum Width Min width 3 2.2 Active to Active Spacing Spacing 3 2.3a Source/Drain Active to Well Edge Surround 5 2.3b Source/Drain Active to Well Space Spacing 5 2.4a WellContact(Active) to Well Edge Surround 3 2.4b SubsContact(Active) to Well Spacing Spacing 3 * * 实验所采用的设计规则 表3：多晶硅（Poly）规则 规则 描述 规则类型 lambda 3.1 Poly Minimum Width Min width 2 3.2 Poly to Poly Spacing Spacing 2 3.3 Gate Extension out of Active Extension 2 3.4/4.1 Source/Drain Width Extension 3 3.5 Poly to Active Spacing Spacing 1 * * 实验所采用的设计规则 规则 描述 规则类型 Lambda 7.1a Metal1 Minimum Width Min width 3 7.1b Tight Metal1 Max Width Not exist 7.2a Metal1 to Metal1 Spacing Spacing 3 7.2b Tight Metal1 spacing Spacing 2 7.2c Tight Metal1 space to Metal1 Spacing 2 7.3 Metal1 Overlap of PolyContact Surround 1 7.4 Metal1 Overlap of ActiveContact Surround 1 * * 实验所采用的设计规则 规则 描述 规则类型 lambda 5.1 Poly Contact Exact Size Exact width 2 5.2a FieldPoly Overlap of PolyCnt Surround 1.5 5.2b Not-Exists: PolyCnt_not_on_Poly Not exist 5.3 PolyContact to PolyContact Spacing Spacing 2 6.1 Active Contact Exact Size Exact width 2 6.2 FieldActive Overlap of ActCnt Surround 1.5 6.3 ActCnt to ActCnt Spacing Spacing 2 6.4 Active Contact to Gate Spacing Spacing 2 表5：接触孔规则 * * 实验所采用的设计规则 8.1 Via1 Exact Size Exact width 2 8.2 Via1 to Via1 Spacing Spacing 3 8.3 Metal1 Overlap of Via1 Surround 1 8.4a Via1 to PolyContact Spacing Spacing 2 8.4b Via1 to ActiveContact Spacing Spacing 2 8.5a Via1 to Poly Spacing Spacing 2 8.5b Via1(On Poly) to Poly Edge Spacing 2 8.5c Via1 to Active Spacing Spacing 2 8.5d Via1 (On Active) to Active Edge Spacing 2 * * chrt35DRC manual（pa