VHDL流水线加法器.doc

可编程实验报告 实验报告要求： 1、任务的简单描述 2、画出电路图 3、写出源代码 4、仿真结果 5、分析和讨论 1、3-8译码器 源代码： LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; ENTITY dc38 IS PORT( sel : in std_logic_vector(2 downto 0); y : out std_logic_vector(7 downto 0)); END dc38; ARCHITECTURE behavior OF dc38 IS BEGIN y =WHEN sel = 000 else WHEN sel = 001 else WHEN sel = 010 else WHEN sel = 011 else WHEN sel = 100 else WHEN sel = 101 else WHEN sel = 110 else WHEN sel = 111 else ZZZZZZZZ; END behavior; 仿真结果： 一位全加器 A B CI S CO 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 四级流水加法器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity adder is port( clk,rst : in std_logic; a,b : in std_logic_vector(3 downto 0); sum : out std_logic_vector(3 downto 0); c : out std_logic); end entity adder; architecture depict of adder is signal reg1: std_logic_vector(7 downto 0); signal reg2: std_logic_vector(6 downto 0); signal reg3: std_logic_vector(5 downto 0); begin bit0:process(clk,rst) begin if(rst=1) then reg1 elsif(rising_edge(clk)) then reg1(0)= a(0) xor b(0); reg1(1)= a(0) and b(0); reg1(2)= a(1); reg1(3)= b(1); reg1(4)= a(2); reg1(5)= b(2); reg1(6)= a(3); reg1(7)= b(3); end if; end process bit0; bit1:process(clk,rst) begin if(rst=1) then reg2=0000000; elsif(rising_edge(clk)) then reg2(0)= reg1(0); reg2(1)= reg1(1) xor reg1(2) xor reg1(3); reg2(2)= (reg1(1) and reg1(2))or(reg1(1)and reg1(3))or(reg1(2)and reg1(3)); reg2(6 downto 3)=reg