max10fpga器件体系结构-altera.pdf

MAX 10 FPGA 器件体系结构 2016.05.13 M10-ARCHITECTURE 订阅 反馈 MAX 10 器件包含下面组件： • 逻辑阵列模块(LAB) • 模数转换器 (ADC) • 用户闪存(UFM) • 嵌入式乘法器模块 • 嵌入式存储器模块 (M9K) • 时钟和锁相环 (PLL) • 通用 I/O • 高速 LVDS I/O • 外部存储器接口 • 配置闪存 (CFM) © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark ice and in other countries. All other words and logos dentied as ISO trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance 9001:2008 of its semiconductor products to current specictons in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specictons before relying on any published information and before placing orders for products or services. 101 Innovation Drive, San Jose, CA 95134