MAXreg 10 FPGA 器件体系结构.PDF

® MAX 10 FPGA 器件体系结构 2017.02.21 M10-ARCHITECTURE 订阅 反馈 ® MAX 10 器件的组成如下： • 逻辑阵列模块（LAB） • 模数转换器（ADC ） • 用户闪存（UFM） • 嵌入式乘法器模块 • 嵌入式存储模块（M9K） • 时钟和锁相环（PLL） • 通用 I/O • 高速 LVDS I/O • 外部存储器接口 • 配置闪存（CFM） Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current ISO sptons in accordance with Intels standard warranty, but reserves the right to make changes to any products and services at any time without notice. 9001:2008 Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly Registered agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device sptons before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 101 Innovation Drive, San Jose, CA 95134 M10-ARCHITECTURE 2 逻辑阵列模块 2017.02.21 图1: MAX 10 器件的典型器件平面规划 • 各个 MAX 10 器件中每种模块的数量和位置各不相同。 • 某些 MAX 10 器件可能不包含指定的模块。 时钟 逻辑阵列模块