数字电路英文版第九单元.ppt

KEY TERMS Asynchronous counter A type of counter in which each stage is clocked from the output of the preceding stage. Cascade To connect “end-to-end” as when several counters are connected from the terminal count output of one counter to the enable input of the next counter. Decade Characterized by ten states or values. Decade counter A digital counter having ten states. Recycle To undergo transition from the final or terminal state back to the initial state. Ripple counter An asynchronous counter. Sequence The order in which several things occur in a specified time relationship. Sequential circuit A digital circuit whose logic states follow on a specified time sequence. State diagram A graphic depicition of a sequence of states or values. State machine A logic system exhibiting a sequence of states conditioned by internal logic and external inputs; any sequential circuit exhibiting a specified sequence of states. Terminal count The final state in a counter’s sequence. Synchronous counter A type of counter in which each stage is clocked by the same pulse. Truncated Shortened. Truncated sequence A sequence that does not include all of the possible states of a counter. Up/Down counter A counter that can progress in either direction through a certain sequence. To design in another way To design in another way Design problem 2 sequence detector Consider a synchronous sequential logic circuit that will detect a defined serial pattern appearing on a signal data input. Suppose the serial input to detect is 0110011, with Z becoming a 1 immediately after the last bit appears in the sequence. Design procedure 1. Derive the state diagram. 2. Draw the state table. 3. Assign state variable patterns to states. 4. Draw the assigned state table. 5. Derive the flip-flop input functions, and in our design. 6. Derive the output function of a K-map, and finally. 7. Draw the logic circuit. State table present state Next state