网站大量收购闲置独家精品文档,联系QQ:2885784924

驱动讲义nzy.ppt

  1. 1、本文档共36页,可阅读全部内容。
  2. 2、有哪些信誉好的足球投注网站(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
驱动讲义nzy

RK27驱动软件 内容提要 内容提要 RK27XX 系列资源列表(1) RK27XX 系列资源列表(2) RK27XX 芯片架构 系统特性 System Operation ? Dual Core Architecture (ARM7EJC+DSP) ? Support system boot sequentially from ARM7EJC to DSP ? Selectable JTAG debug method ? ARM7EJC debug only ? DSP debug only ? ARM7EJC+DSP dual core debug ? Selectable booting method ? Boot from NOR Flash ? Boot from Embedded ROM ? Internal memory space ? DSP IMEM 32Kwords ? DSP DMEM 32Kwords ? ARM7EJC Embedded Sync SRAM 4Kbytes ? ARM7EJC Embedded Boot ROM 8Kbytes 内容提要 LCD Controller LCDC Unit is a controller interface to LCD panel, including a 2048X32bit SRAM. Key features Compatible MCU and RGB interface。 Compatible 8bits series and 24bits parallel RGB interface. Support delta RGB interface panel. Support YUV or RGB image source data input relatively in line. Support 8 grade alpha operations. Support even/odd field mode. Support 4:2:2 or 4:2:0 YUV source data input. Support 16bits or 24bits RGB source data input. Support scale base on YUV source. Support MCU buffer write and bypass mode. DMA 系统中有3个独立的DMA模块 ? A2A DMA --- 用于总线间数据传输 ? HDMA --- 用于音频数据传输 ? DW DMA --- 用于视频和LCD数据传输 A2A DMA ? Integrated between AHB BUS0 and AHB BUS1 ? Provide AHB-to-AHB bus protocol translation ? Support AHB-to-AHB DMA or Single AHB DMA ? Two DMA Channels support ? On-the-fly mode between two level bus support ? 4 hardware request handshaking support ? Support hardware and software trigger DMA transfer mode HDMA ? DW DMA ? Integrated in AHB BUS1 ? Four DMA Channels support ? 8 hardware request handshaking support ? Support hardware and software trigger DMA transfer mode ? Build-in 4 data FIFO : 64bytes/64bytes/64bytes/64bytes ? Scatter/Gather transfer support ? LLP transfer support ? Two master for on-the-fly support DW DMA ? Integrated in AHB BUS1 ? Four DMA Channels support ? 8 hardware request handshaking support ? Support hardware and software trigger DMA transfer mode ? Build-in 4 data FIFO : 64bytes/64bytes/64bytes/64bytes ? Scatter/Gat

文档评论(0)

xcs88858 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

版权声明书
用户编号:8130065136000003

1亿VIP精品文档

相关文档