andgap集成电路掩模版图设计.doc

PAGE 摘 要 集成电路掩模版图设计是实现集成电路制造所必不可少的设计环节，它不仅关系到集成电路的功能是否正确，而且也会极大程度地影响集成电路的性能、成本与功能。模拟版图设计对电路的性能有更高的要求，要求模拟版图设计者使用更多的方法去优化电路，减小电路的寄生参数，提高电路的稳定性。 本论文首先介绍半导体制造技术、模拟IC版图设计的基本流程，然后通过bandgap的单元版图设计到整体版图设计流程具体介绍模拟版图设计的一些细节和一些问题的解决方法，最后介绍一些平面布局及封装技术。 本设计使用cadence 全定制设计工具IC610进行bandgap的版图设计，其后使用diva对版图进行物理验证。 关键词：版图；bandgap；cadence；IC Abstract IC mask layout are essential to achieve the design of integrated circuit manufacturing sectors, it is not only related to the ICs functions are correct, but also great extent affect IC performance, cost and functionality. Simulate the performance of the circuit layout have higher demands to analog layout designers to use more methods to optimize the circuit, reducing the parasitic circuit parameters, to improve the stability.  This paper first introduces the semiconductor manufacturing technology, analog IC layout design of the basic flow, then bandgap of the cell layout to the overall layout design process specific analog layout design introduced some of the details and some solution to the problem, and finally introduce some layout and packaging technology.  The design of full custom design using cadence tools IC610 for bandgap of the layout design, then use the diva of the physical layout verification. Keywords: layout; bandgap; cadence; physical verification 目 录 TOC \o 1-3 \h \z \u HYPERLINK \l _Toc265398095 1 绪论 PAGEREF _Toc265398095 \h 1 HYPERLINK \l _Toc265398096 2 工艺简介 PAGEREF _Toc265398096 \h 3 HYPERLINK \l _Toc265398097 2.1 光刻 PAGEREF _Toc265398097 \h 3 HYPERLINK \l _Toc265398098 2.2 掺杂 PAGEREF _Toc265398098 \h 4 HYPERLINK \l _Toc265398099 2.3 淀积 PAGEREF _Toc265398099 \h 4 HYPERLINK \l _Toc265398100 2.4 CMOS工艺 PAGEREF _Toc265398100 \h 4 HYPERLINK \l _Toc265398101 2.5 PNP工艺 PAGEREF _Toc265398101 \h 6 HYPERLINK \l _Toc265398103 2.6 POLY电阻工艺 PAGEREF _Toc265398103 \h 7 HYPERLINK \l _Toc265398104 3 Cadence简介 PAGEREF _Toc265398104 \h 9 HYPERLINK \l _Toc265398105 4 bandgap版图设计流程 PAGER