StratixV器件中的时钟网络和PLL.pdf

Stratix V器件中的时钟网络和PLL 4 2014.01.10 SV51005 订阅 反馈 本章节介绍了Stratix®V器件中分级时钟网络与锁相环(PLL)的高级特性。Quartus®II软件不需要外部 器件来使能PLL及其功能。 相关链接 Stratix V器件手册：已知问题 列出了对Stratix V器件手册章节规划的更新。 时钟网络 Stratix V器件包括层次化的以下时钟网络： • 全局时钟(GCLK)网络 • 局域时钟(RCLK)网络 • 外围时钟(PCLK)网络 Stratix V器件中的时钟资源 表4-1: Stratix V器件中的时钟资源 时钟资源 器件 可用的资源数量 时钟资源的来源 48个单端或24个差 时钟输入管脚 全部 CLK[0..23][p,n]管脚 分对 CLK[0..23][p,n]管脚，PLL时 GCLK网络 全部 16 钟输出和逻辑阵列 CLK[0..23][p,n]管脚，PLL时 RCLK 网络 全部 92 钟输出和逻辑阵列 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes Registered no responsibility or liability arising out of the applicat